In recent years semiconductor device fabrication has become complex, involving increasing numbers of process steps. In addition, the individual process steps themselves have become more complex, including processes that provide for multi-layer interconnections.
Not only is semiconductor device fabrication becoming more complex, but also semiconductor device feature sizes are becoming smaller and smaller. Circuit patterns for semiconductor devices are generally formed on the surface of the wafer using high-resolution optical systems. Such high-resolution optical systems frequently use short-wavelength light and high numerical aperture optics. In such high-resolution optical systems, the depth of focus of the optical system is small and wafer surface irregularities cause errors in the projected patterns. Therefore, the accurate transfer of circuit patterns to a semiconductor wafer requires that the wafer surface be flat.
Providing a flat surface to a wafer or similar type of workpiece is challenging. The required degree of flatness can be less than a fraction of a wavelength of light. Wafers generally have large cross-sections and small thicknesses and accordingly are not mechanically stiff. Therefore, the flatness of a wafer surface is easily disturbed by even small forces applied to the wafer.
Flatness errors associated with the small thickness of the wafer tend to produce local curvature of the wafer surface and variations in wafer thickness. The flatness errors associated with wafer curvature tend to be gradual, extending distances across the wafer surface that are greater than the wafer thickness.
Other flatness errors are possible as well. Some advanced fabrication processes alter the surface of the semiconductor wafer so that the wafer surface is not flat, even if the surface was flat before fabrication began. For example, the deposition of a conducting or insulating strip on the wafer surface creates a vertical step in the wafer surface. The vertical step causes defects in subsequent fabrication steps. For example, a conducting layer that crosses a vertical step can suffer a vertical break, resulting in a large increase in resistance, an open circuit, or reduced current capacity. An insulating layer on top of a vertical step can have reduced resistance, permitting increased leakage currents. To prevent these defects, a flat wafer surface must be maintained during processing.
FIGS. 14(a), 14(b), and 14(c) show typical flatness errors and the correction of these errors with respect to wafers and similar workpieces; the flatness errors of FIG. 14 are typical of flatness errors that result from wafer processing. FIG. 14(a) shows the correction of a flatness error resulting from deposition of an insulating layer 401 on a wafer. The insulating layer 401 is typically borophosphosilicate glass (BPSG), tetraethylorthosilicate-silicon dioxide (TEOS-SiO.sub.2)), or another insulating material. FIG. 14(b) shows the correction of a flatness error near a conductor layer 402 that connects to other layers. Portions of the conductor layer 402 are removed, flattening the surface. Typical conducting layers are metallic layers of tungsten, aluminum, or copper. FIG. 14(c) shows the removal of excess metal in a conducting layer 403 associated with an embedded conductor (Damascene Process).
Flatness errors such as those of FIGS. 14(a)-(c) are conventionally removed using a chemical-mechanical polishing or chemical-mechanical planarization technique ("CMP"). FIG. 15 shows a conventional semiconductor polishing apparatus for semiconductor wafers using the CMP technique. FIGS. 15(a) and 15(b) are a side elevational view and plan view, respectively, of the semiconductor polishing apparatus.
The polishing apparatus of FIGS. 15(a)-15(b) has a polishing pad 200 fixed to a polishing wheel 100. A wafer carrier 301 holds a wafer 300 and a pressure mechanism (not shown in the figure) applies a pressure 110 that forces the wafer carrier 301 and the wafer 300 against the polishing pad 200. The polishing wheel 100 rotates while a polishing slurry 202 drips from a dispenser 201. The wafer carrier 301 both rotates about its axis and slides across the polishing pad 200, thereby polishing the surface of the wafer 300. The polishing pad 200 is typically a felt sheet with a two-layer structure consisting of a lower layer of non-woven cloth and an upper layer of a micro-porous polyurethane foam.
Various methods have been used for determining the state of polish of the wafer 300 and thereby determining when to stop polishing. The state of polish of the wafer 300 at which polishing should stop is called the endpoint. Methods for controlling attainment of the endpoint include controlling the polishing time, detecting changes in the torque required to rotate the wafer carrier 301 (typically by measuring the electric current drawn by the motor that rotates the wafer carrier 301), and detecting changes in the frictional sound caused by polishing.
Optical methods of endpoint detection have also been used. In conventional optical endpoint detection, holes are provided in the table 100 and the polishing pad 200, through which holes a laser beam irradiates the wafer 300. A portion of the laser beam is reflected by the wafer 300; the reflected light is detected and used to assess the state of polish of the wafer 300.
The CMP technique has various drawbacks. CMP polishing tends to over-polish the edges of the wafer 300. The wafer 300 is frequently deformed when pressure is applied to the wafer 300 during polishing. Particles and other irregularities in the adhesive layer binding the polishing pad 200 to the polishing wheel 100 cause additional wafer deformations. The polishing pad 200 tends to clog and therefore the polishing pad 200 must be dressed or ground frequently if it is to continue polishing effectively. The polishing pad 200 tends to wear out, requiring frequent replacement. As a result, the CMP technique using the polishing pad 200 is generally unable to polish the wafer 300 as smooth and flat as required. In addition, the polishing pad 200 requires frequent dressing or replacement during use, slowing wafer processing.
Furthermore, it is difficult to observe and measure the state of polish of the wafer 300 during the polishing process. When conventional optical endpoint detection is used, the required hole in the polishing lap and polishing wheel make achieving wafer flatness even more difficult. Other conventional endpoint-determination methods rely on secondary indicators (e.g., sound or torque) of the state of polish of the wafer 300. Using these methods the wafer 300 is frequently polished excessively or polishing is interrupted before the desired endpoint is reached. Interrupting polishing for inspection only to begin polishing again is inconvenient and slows wafer processing.
Therefore, it is advantageous to determine when to stop polishing ("endpoint detection") during polishing but conventional methods do not reliably permit such endpoint detection.